Abstract: In view of the shortcoming of conventional CMOS current multiplier/divider in low linearity and low frequency,a novel CMOS current modemultiplier/divider based on MOS Translinear rule,with square-root and squarer/divider circuit for core circuit,is proposed.HSPICE simulation test using TSMC's0.35 μm CMOS process model show a -3 dB bandwidth of 35.1 MHz for the circuit,working at a supply voltage of 3 V,and its static power consumption is 202.68 μW,output current range 0~25.1 μA,nonlinear error 0.85% and total harmonicdistortion 0.14%.Compared with the multipliers/dividers designed by Tanno,Lopez,et al.,the proposed multiplier/divider circuit has many advantages,using-3 dB bandwidth,reduced power consumption,reduced power supply voltage,improvedlinearity,raised accuracy,and a relatively more advanced 0.35 μm CMOS technology,and saving chip area.

Key words: square-root circuit, squarer/divider circuit, multiplier/divider, translinear principle