广西师范大学学报(自然科学版) ›› 2012, Vol. 30 ›› Issue (2): 12-16.

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新型高频高线性CMOS跨导线性电流模乘/除法器设计

解鸿国, 宋树祥   

  1. 广西师范大学电子工程学院,广西桂林541004
  • 收稿日期:2012-03-01 出版日期:2012-06-20 发布日期:2018-12-03
  • 通讯作者: 宋树祥(1970—),男,湖南双峰人,广西师范大学副教授,博士。E-mail:songshuxiang@mailbox.gxnu.edu.cn
  • 基金资助:
    国家自然科学基金资助项目(61061006)

Novel High-frequency High-linear CMOS Translinear Current-mode Multiplier/Divider

XIE Hong-guo, SONG Shu-xiang   

  1. College of Electronic Engineering,Guangxi Normal University,Guilin Guangxi 541004,China
  • Received:2012-03-01 Online:2012-06-20 Published:2018-12-03

摘要: 针对传统CMOS电流乘除法器存在线性度不高、工作频率低等缺点,提出一种以平方根电路、平方/除法器电路为核心的基于MOS管跨导线性原理的新型高频高线性CMOS电流模乘/除法器。在TSMC 0.35 μm CMOS集成工艺下进行HSPICE仿真测试表明:该电路在3 V电源电压下,-3 dB带宽可达到35.1 MHz,电源静态功耗为202.68 μW,输出电流为0~25.1 μA,非线性误差为0.85%,总谐波失真为0.14%。本文提出的乘除法器电路与Tanno、Lopez等提出的基于跨导线性原理的乘除法器电路相比,优点在于-3 dB带宽提高了,功耗降低了,电源电压降低了,线性度提高了,精度提高了,并且采用了相对更先进的0.35 μm CMOS工艺,可缩小芯片面积,节约成本。

关键词: 平方根电路, 平方/除法器电路, 乘法器/除法器, 跨导线性原理

Abstract: In view of the shortcoming of conventional CMOS current multiplier/divider in low linearity and low frequency,a novel CMOS current modemultiplier/divider based on MOS Translinear rule,with square-root and squarer/divider circuit for core circuit,is proposed.HSPICE simulation test using TSMC's0.35 μm CMOS process model show a -3 dB bandwidth of 35.1 MHz for the circuit,working at a supply voltage of 3 V,and its static power consumption is 202.68 μW,output current range 0~25.1 μA,nonlinear error 0.85% and total harmonicdistortion 0.14%.Compared with the multipliers/dividers designed by Tanno,Lopez,et al.,the proposed multiplier/divider circuit has many advantages,using-3 dB bandwidth,reduced power consumption,reduced power supply voltage,improvedlinearity,raised accuracy,and a relatively more advanced 0.35 μm CMOS technology,and saving chip area.

Key words: square-root circuit, squarer/divider circuit, multiplier/divider, translinear principle

中图分类号: 

  • TN432
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