12 bit 100 MS/s 逐次逼近型模数转换器设计

doi:10.16088/j.issn.1001-6600.2026012401

摘要/Abstract

摘要： 为了解决高速、中高精度模数转换器在采样非线性失真、电容阵列开关功耗大、面积与能效难以兼顾等问题,本文提出一种基于电荷再分配原理的12位100 MS/s逐次逼近型模数转换器(successive approximation register analog-to-digital converter, SAR ADC),采用65 nm CMOS工艺实现。采用自举开关抑制输入信号在采样阶段的非线性失真,结合改进型单调开关算法,优化二进制加权电容阵列的开关能耗与面积,选用动态比较器保证更低功耗。仿真结果表明,在100 MS/s采样速率下,该ADC在奈奎斯特输入频率下实现64.5 dB的信噪失真比(SNDR)、74.53 dB的无杂散动态范围(SFDR),对应有效位数(ENOB)达10.4 位。在1.2 V电源电压下,总功耗仅为4.8 mW,展现出其在高速中精度应用场景中的优异性能与能效竞争力。

关键词: 逐次逼近型模数转换器, 动态比较器, 栅压自举开关, 电容阵列, 低功耗

Abstract: To address issues such as sampling nonlinearity, high power consumption of capacitor array switching, and the trade-off between area and energy efficiency in high-speed and medium-to-high-precision analog-to-digital converters (ADCs), this paper proposes a 12-bit 100 MS/s successive approximation register ADC (SAR ADC) based on charge redistribution principles, implemented in 65 nm CMOS technology. A bootstrap switch is employed to mitigate input signal nonlinearity during the sampling phase, while an improved monotonic switching algorithm optimizes the switching power consumption and area of the binary-weighted capacitor array. A dynamic comparator is selected to ensure lower power consumption. Simulation results demonstrate that at a 100 MS/s sampling rate, the ADC achieves a signal-to-noise and distortion ratio (SNDR) of 64.5 dB and a spurious-free dynamic range (SFDR) of 74.53 dB at the Nyquist input frequency, corresponding to an effective number of bits (ENOB) of 10.4. With a power supply voltage of 1.2 V, the total power consumption is only 4.8 mW, showcasing excellent performance and energy efficiency competitiveness in high-speed medium-precision applications.

Key words: SAR ADC, dynamic comparator, gate voltage bootstrapped switch, capacitor array, low power consumption

中图分类号: TN432;TN792

陈庚, 宋树祥, 蒋品群, 蔡超波. 12 bit 100 MS/s 逐次逼近型模数转换器设计[J]. 广西师范大学学报（自然科学版）, 2026, 44(5): 38-48.

Chen Geng, Song Shuxiang, Jiang Pinqun, Cai Chaobo. Design of 12 bit 100 MS/s successive approximation analog-to-digital converter[J]. Journal of Guangxi Normal University(Natural Science Edition), 2026, 44(5): 38-48.

参考文献

[1] 刘翼霖. 高精度分段式逐次逼近型模数转换器关键技术研究[D]. 成都: 电子科技大学, 2025.
[2] 朱樟明, 刘术彬. 高性能模数转换器技术挑战与发展趋势[J]. 中国科学(信息科学), 2024, 54(1): 48-57. DOI: 10.1360/SSI-2023-0310.
[3] Kang H, Asmat Ali Shah S, Kim H. An energy-efficient 12b 2.56 MS/s SAR ADC using successive scaling of reference voltages[J]. Computers, Materials & Continua, 2022, 72(1): 2127-2139. DOI: 10.32604/cmc.2022.025798.
[4] 都文和, 韩波, 宋昊洋, 等. 一种基于冗余位结构CDAC的12 bit SAR ADC[J]. 北华大学学报(自然科学版), 2024, 25(6): 825-832. DOI: 10.11713/j.issn.1009-4822.2024.06.023.
[5] 雷鹏. 高精度逐次逼近型模数转换器关键性技术研究与设计[D]. 成都: 电子科技大学, 2022.
[6] Li X Y, Wang R D, He L L, et al. A high-speed 8-bit single-channel SAR ADC with tailored bit intervals and split capacitors[J]. Electronics, 2025, 14(10): 2032. DOI: 10.3390/electronics14102032.
[7] Goodall W M. Telephony by pulse code modulation[J]. Bell System Technical Journal, 1947, 26(3): 395-409. DOI: 10.1002/j.1538-7305.1947.tb00902.x.
[8] Mccreary J L, Gray P R. All-MOS charge redistribution analog-to-digital conversion techniques. I[J]. IEEE Journal of Solid-State Circuits, 1975, 10(6): 371-379. DOI: 10.1109/JSSC.1975.1050629.
[9] 丁召明, 周雄, 李强. 低功耗逐次逼近寄存器模数转换器综述[J]. 微电子学, 2018, 48(3): 401-405, 415. DOI: 10.13911/j.cnki.1004-3365.170332.
[10] Harp J A,Zhou C,Bi Y,et al. A 26 W 8 bit 10 MS/s Asynchronous SAR ADC for Low Energy Radios[J]. IEEE Journal of Solid-State Circuits,2011,46(7):1585-1595. DOI: 10.1109/JSSC.2011.2143870.
[11] Razavi B. The bootstrapped switch a circuit for all seasons[J]. IEEE Solid-State Circuits Magazine, 2015, 7(3): 12-15. DOI: 10.1109/MSSC.2015.2449714.
[12] Liu Q, Shu W, Chang J S. A 1-GS/s 11-bit SAR-assisted pipeline ADC with 59-dB SNDR in 65-nm CMOS[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2018, 65(9): 1164-1168. DOI: 10.1109/TCSII.2018.2814581.
[13] Ramkaj A, Tavernier F, Steyaert M. Fast switch bootstrapping for GS/s high-resolution analog-to-digital converter[C]//2015 11th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME). Piscataway,NJ:IEEE, 2015: 73-76. DOI: 10.1109/PRIME.2015.7251337.
[14] 周金权,郭仲杰,许睿明.高速CMOS图像传感器列级Pipelined-SAR ADC研究[J/OL].哈尔滨工业大学学报,1-17[2026-04-02].https://link.cnki.net/urlid/23.1235.T.20260126.1436.007.
[15] 田芮谦, 宋树祥, 刘振宇, 等. 逐次逼近型模数转换器研究进展[J]. 广西师范大学学报(自然科学版), 2022, 40(5): 24-35. DOI: 10.16088/j.issn.1001-6600.2022022704.
[16] Ginsburg B P, Chandrakasan A P. An energy-efficient charge recycling approach for a SAR converter with capacitive DAC[C]//2005 IEEE International Symposium on Circuits and Systems. Piscataway,NJ:IEEE, 2005: 184-187. DOI: 10.1109/ISCAS.2005.1464555.
[17] Wei C, Wei R S, Zhou Q K, et al. A power-area efficient new merged capacitor switching scheme for SAR ADC[C]//2024 31st IEEE International Conference on Electronics, Circuits and Systems (ICECS). Piscataway,NJ:IEEE, 2025: 1-4. DOI: 10.1109/ICECS61496.2024.10849294.
[18] 陈海波.0.35μm CMOS工艺下12位30MS/s SAR ADC的设计[D].南京:东南大学,2016.
[19] 曹超, 马瑞, 朱樟明, 等. 高精度 SARADC 非理想因素分析及校准方法[J]. 西安电子科技大学学报(自然科学版), 2015, 42(6): 61-65, 87. DOI: 10.3969/j.issn.1001-2400.2015.06.011.
[20] Yi T G, Li Z B, Du B, et al. A noise shaping SAR ADC with kT/C noise cancellation and mismatch error shaping[C]//2024 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA). Piscataway,NJ:IEEE, 2025: 226-227. DOI: 10.1109/ICTA64028.2024.10860317.
[21] Nuzzo P, De Bernardinis F, Terreni P, et al. Noise analysis of regenerative comparators for reconfigurable ADC architectures[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2008, 55(6): 1441-1454. DOI: 10.1109/TCSI.2008.917991.
[22] Rabaey J M, Chandrakasan A P, NikoliC′, B. Digital integrated circuits: a design perspective[M]. Upper Saddle River, N.J.: Pearson Education,2003.
[23] Yu A, Bankman D, Zheng K, et al. Understanding metastability in SAR ADCs: part II: asynchronous[J]. IEEE Solid-State Circuits Magazine, 2019, 11(3): 16-32. DOI: 10.1109/MSSC.2019.2922890.
[24] Chen S M, Brodersen R W. A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-μm CMOS[J]. IEEE Journal of Solid-State Circuits, 2006, 41(12): 2669-2680. DOI: 10.1109/jssc.2006.884231.
[25] 罗扎. 模拟CMOS集成电路设计[M]. 北京:清华大学出版社, 2005.
[26] Thomas A, Tressha A, Priyadarshini K V, et al. A 10-bit 45.5-MS/s asynchronous SAR ADC with a DCDAC switching technique in 45nm CMOS[C]//2025 International Conference on Electrical, Electronics, and Computer Science with Advance Power Technologies-A Future Trends (ICE2CPT). Piscataway,NJ:IEEE,2026: 1-7. DOI: 10.1109/ICE2CPT66440.2025.11340244.
[27] Ginsburg B P, Chandrakasan A P. Dual time-interleaved successive approximation register ADCs for an ultra-wideband receiver[J]. IEEE Journal of Solid-State Circuits, 2007, 42(2): 247-257. DOI: 10.1109/JSSC.2006.889372.
[28] Omran H, Alahmadi H, Salama K N. Matching properties of femtofarad and sub-femtofarad MOM capacitors[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2016, 63(6): 763-772. DOI: 10.1109/TCSI.2016.2537824.
[29] 薛彪.12比特100 MS/s低功耗SAR ADC的设计[D].南京:东南大学,2024.DOI: 10.27014/d.cnki.gdnau.2024.005535.
[30] Tseng W H, Lee W L, Huang C Y, et al. A 12-bit 104 MS/s SAR ADC in 28 nm CMOS for digitally-assisted wireless transmitters[J]. IEEE Journal of Solid-State Circuits, 2016, 51(10): 2222-2231. DOI: 10.1109/JSSC.2016.2582861.
[31] He W B, Ye F, Ren J Y. A fast response reference voltage buffer for 12b 200MS/s SAR ADC[C]//2020 IEEE 63rdInternational Midwest Symposium on Circuits and Systems (MWSCAS). Piscataway,NJ:IEEE, 2020: 1-4. DOI: 10.1109/MWSCAS48704.2020.9184609.
[32] Li M X, Yao Y T, Hu B, et al. A 6.94-fJ/conversion-step 12-bit 100-MS/s asynchronous SAR ADC exploiting split-CDAC in 65-nm CMOS[J]. IEEE Access, 2021, 9: 77545-77554. DOI: 10.1109/ACCESS.2021.3079406.
[33] 王一飞, 宋树祥, 蔡超波, 等. 14位低功耗逐次逼近型模数转换器设计[J]. 广西大学学报(自然科学版), 2022, 47(1): 144-153. DOI: 10.13624/j.cnki.issn.1001-7445.2022.0144.
[34] Liu F M, Ding J, Wu J F, et al. A digital front-end self-calibration algorithm for SAR ADC[C]//2025 IEEE 16th International Conference on ASIC (ASICON). Piscataway,NJ:IEEE, 2026: 1-4. DOI: 10.1109/ASICON66040.2025.11326425.

Metrics

Viewed

Full text

Abstract

Cited

Shared

Discussed