12 bit 100 MS/s 逐次逼近型模数转换器设计

doi:10.16088/j.issn.1001-6600.2026012401

Abstract

Abstract: To address issues such as sampling nonlinearity, high power consumption of capacitor array switching, and the trade-off between area and energy efficiency in high-speed and medium-to-high-precision analog-to-digital converters (ADCs), this paper proposes a 12-bit 100 MS/s successive approximation register ADC (SAR ADC) based on charge redistribution principles, implemented in 65 nm CMOS technology. A bootstrap switch is employed to mitigate input signal nonlinearity during the sampling phase, while an improved monotonic switching algorithm optimizes the switching power consumption and area of the binary-weighted capacitor array. A dynamic comparator is selected to ensure lower power consumption. Simulation results demonstrate that at a 100 MS/s sampling rate, the ADC achieves a signal-to-noise and distortion ratio (SNDR) of 64.5 dB and a spurious-free dynamic range (SFDR) of 74.53 dB at the Nyquist input frequency, corresponding to an effective number of bits (ENOB) of 10.4. With a power supply voltage of 1.2 V, the total power consumption is only 4.8 mW, showcasing excellent performance and energy efficiency competitiveness in high-speed medium-precision applications.

Key words: SAR ADC, dynamic comparator, gate voltage bootstrapped switch, capacitor array, low power consumption

CLC Number: TN432;TN792

Chen Geng, Song Shuxiang, Jiang Pinqun, Cai Chaobo. Design of 12 bit 100 MS/s successive approximation analog-to-digital converter[J].Journal of Guangxi Normal University(Natural Science Edition), 2026, 44(5): 38-48.

References

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Design of 12 bit 100 MS/s successive approximation analog-to-digital converter

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