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广西师范大学学报(自然科学版) ›› 2022, Vol. 40 ›› Issue (5): 24-35.doi: 10.16088/j.issn.1001-6600.2022022704
田芮谦, 宋树祥*, 刘振宇, 岑明灿, 蒋品群, 蔡超波
TIAN Ruiqian, SONG Shuxiang*, LIU Zhenyu, CEN Mingcan, JIANG Pinqun, CAI Chaobo
摘要: 逐次逼近型模数转换器(successive approximation register analog-to-digital converter,SAR ADC)已占据中等速度和精度ADC的主要市场,其采样频率可达5 MHz,分辨率通常为8~16位。在保持其低功耗的固有优势下,SAR ADC设计面临更高速和更高精度的挑战。本文概述近年来逐次逼近型模数转换器的研究现状和先进技术,对电容阵列开关切换技术、比较器和校准方法进行归纳与讨论;对比了结合不同开关策略的电容阵列DAC性能;提出了适用于不同场景的比较器结构;对高速度、高精度、低功耗的SAR ADC研究进行了展望。
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[1]CHUNG Y H, YEN C W, TSAI P K, et al. A 12-bit 40-MS/s SAR ADC with a fast-binary-window DAC switching scheme[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2018, 26(10): 1989-1998. [2]刘滢浩,刘宏,徐乐,等.一种Vcm-Based10位16M采样率低功耗逐次逼近型模数转换器[J].微电子学与计算机,2017,34(11):99-103. [3]WANG S H, HUNG C C. A 0.3 V 10 b 3 MS/s SAR ADC with comparator calibration and kickback noise reduction for biomedical applications[J]. IEEE Transactions on Biomedical Circuits and Systems, 2020, 14(3): 558-569. [4]PILIPKO M M, MANOKHIN M E. Design of a low-power 12-bit SAR ADC[C]// 2019 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus). Piscataway,NJ: IEEE, 2019: 129-131. [5]SHAH A, SAHOO B D. An 8 b 5-GS/s CMOS SAR ADC with speed optimized SAR logic[C]// 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS). Piscataway,NJ: IEEE, 2017: 1465-1468. [6]HU B J, ZHANG S F, ZHOU X, et al. A sampling speed enhancement technique for near-threshold SAR ADCs[C]// 2021 IEEE International Symposium on Circuits and Systems (ISCAS). Piscataway,NJ: IEEE, 2021: 1-4. [7]SAVITHAM, REDDY R V S. 14-bit low power successive approximation ADC using two step split capacitive array DAC with multiplexer switching[C]// 2018 Second International Conference on Advances in Electronics, Computers and Communications (ICAECC). Piscataway,NJ: IEEE, 2018: 1-4. [8]LIU S B, SHEN Y, ZHU Z M. A 12-Bit 10 MS/s SAR ADC with high linearity and energy-efficient switching[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2016, 63(10): 1616-1627. [9]KAO C C, HSIEH S E, HSIEH C C. A 0.5 V 12-bit SAR ADC using adaptive timedomain comparator with noise optimization[C]// 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC). Piscataway,NJ: IEEE, 2017: 213-216. [10]ZHANG H, WANG X H, ZHANG L, et al. A 10-bit 120-MS/s SAR ADC in 90 nm CMOS with redundancy compensation[C]// 2018 IEEE MTT-S International Wireless Symposium (IWS). Piscataway,NJ: IEEE, 2018: 1-3. [11]CHENG Y S, HU H J, CHANG S J. A 2-GS/s 8 B flash-SAR time-interleaved ADC with background offset calibration[C]// 2019 IEEE International Symposium on Circuits and Systems (ISCAS). Piscataway,NJ: IEEE, 2019: 1-5. [12]ZHANG Q H, NING N, LI J, et al. A high area-efficiency 14-bit SAR ADC with hybrid capacitor DAC for array sensors[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2020, 67(12): 4396-4408. [13]GUO W X, WU J F. A 10 MS/s 16 bit SAR ADC achieving 100 dB SFDR and 90 dB SNDR in 0.18 um CMOS[C]// 2021 IEEE 5th Advanced Information Technology, Electronic and Automation Control Conference (IAEAC). Piscataway,NJ: IEEE, 2021: 974-978. [14]GINSBURG B P, CHANDRAKASAN A P. An energy-efficient charge recycling approach for a SAR converter with capacitive DAC[C]// 2005 IEEE International Symposium on Circuits and Systems. Piscataway,NJ: IEEE, 2005: 184-187. [15]CHANG Y K, WANG C S, WANG C K. A 8-bit 500-KS/s low power SAR ADC for bio-medical applications[C]// 2007 IEEE Asian Solid-State Circuits Conference. Piscataway,NJ: IEEE, 2007: 228-231. [16]LIU C C, CHANG S J, HUANG G Y, et al. A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure[J]. IEEE Journal of Solid-State Circuits, 2010, 45(4): 731-740. [17]HONG X, YANG C C, ZHANG X J. An energy-efficient SAR ADC with a partial-monotonic capacitor switching technique[C]// 2017 IEEE 2nd Advanced Information Technology, Electronic and Automation Control Conference (IAEAC). Piscataway,NJ: IEEE, 2017: 2050-2054. [18]TUNG W, HUANG S C. An energy-efficient 11-bit 10-MS/s SAR ADC with monotonie switching split capacitor array[C]// 2018 IEEE International Symposium on Circuits and Systems (ISCAS). Piscataway,NJ: IEEE, 2018: 1-5. [19]GATADE S, NAGBHUSHAN M. A design of 8 bit SAR ADC using monotonie capacitive switching procedure in 90nm[C]// 2016 International Conference on Circuits, Controls, Communications and Computing (I4C). Piscataway,NJ: IEEE, 2016: 1-5. [20]XING D Z, ZHU Y, CHAN C H, et al. Seven-bit 700-MS/s four-way time-interleaved SAR ADC with partial Vcm-based switching[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017, 25(3): 1168-1172. [21]梁宇华.低功耗逐次逼近型CMOS模数转换器的研究[D].西安:西安电子科技大学,2015. [22]FU Z Y, TANG X, LI D X, et al. A 10-bit 2 MS/s SAR ADC using reverse VCM-based switching scheme[C]// 2016 IEEE International Symposium on Circuits and Systems (ISCAS). Piscataway,NJ: IEEE, 2016: 1030-1033. [23]RAJENDRAN R, RAMAKRISHNA P V. A design of 6-bit 125-MS/s SAR ADC in 0.13-μm MM/RF CMOS process[C]// 2012 International Symposium on Electronic System Design (ISED). Piscataway,NJ: IEEE, 2012: 23-27. [24]HUANG G Y, CHANG S J, LIU C C, et al. 10-bit 30-MS/s SAR ADC using a switchback switching method[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2013, 21(3): 584-588. [25]SANYAL A, SUN N. A very high energy-efficiency switching technique for SAR ADCs[C]// 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS). Piscataway,NJ: IEEE, 2013: 229-232. [26]KHORAMI A, SHARIFKHANI M. An ultra low-power digital to analog converter for SARADCs[C]// 2017 29th International Conference on Microelectronics (ICM). Piscataway,NJ: IEEE, 2017: 1-4. [27]SANYAL A, SUN N. An energy-efficient low frequency-dependence switching technique for SAR ADCs[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2014, 61(5): 294-298. [28]DENG L, YANG C, ZHAO M L, et al. A 12-bit 200KS/s SAR ADC with a mixed switching scheme and integer-based split capacitor array[C]// 2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS). Piscataway,NJ: IEEE, 2013: 1-4. [29]WANG H Y, WANG S Y, YUAN Y D, et al. Low power consumption and low area capacitor array for 16-bit 1-MS/s SAR ADC[C]// 2018 IEEE 3rd Advanced Information Technology, Electronic and Automation Control Conference (IAEAC). Piscataway,NJ: IEEE, 2018: 1003-1006. [30]LAI W C, HUANG J F, LIN W J. 1 MS/s low power successive approximations register ADC for 67-fJ/conversion-step[C]// 2012 IEEE Asia Pacific Conference on Circuits and Systems. Piscataway,NJ: IEEE, 2012: 260-263. [31]XIE L, HAN X F, ZHANG H C, et al. A 12 bit 16 MS/s asynchronous SAR ADC with speed-enhanced comparator and TSPC latch[C]// 2019 IEEE 4th International Conference on Integrated Circuits and Microsystems (ICICM). Piscataway,NJ: IEEE, 2019: 104-108. [32]MENG X Y, KONG W H, YANG H F, et al. A 1.8-GS/s 6-bit two-step SAR ADC in 65-nm CMOS[C]// 2021 IEEE International Symposium on Circuits and Systems (ISCAS). Piscataway,NJ: IEEE, 2021: 1-4. [33]BANDLA K, HARIKRISHNAN A, PAL D. Design of low power, high speed, low offset and area efficient dynamic-latch comparator for SAR-ADC[C]// 2020 International Conference on Innovative Trends in Communication and Computer Engineering (ITCE). Piscataway,NJ: IEEE, 2020: 299-302. [34]SAISUNDAR S, CHEONG J H, JE M. A 1.8 V 1 MS/s rail-to-rail 10-bit SAR ADC in 0.18 μm CMOS[C]// 2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT). Piscataway,NJ: IEEE, 2012: 83-85. [35]LJEHANI N A, ABBAS M. Rail to rail comparator for SAR ADC in biomedical applications[C]// 2021 28th International Conference on Mixed Design of Integrated Circuits and System. Piscataway,NJ: IEEE, 2021: 137-140. [36]OZ M, BONIZZONI E, MALOBERTI F, et al. A rail-to-rail CMOS voltage comparator with programmable hysteresis[C]// 2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS). Piscataway,NJ: IEEE, 2021: 1-4. [37]LI Y F, MAO W, ZHANG Z, et al. An ultra-low voltage comparator with improved comparison time and reduced offset voltage[C]// 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS). Piscataway,NJ: IEEE, 2014: 407-410. [38]XUE G Q, ZHOU N N, HOU D Y. Comparison of frequency-domain electromagnetic responses at different offsets based on exact calculation of grounded-wire source[J]. Radio Science, 2022, 57(1): e2021RS007304. [39]ZHANG H S, ZHU Y, CHAN C H, et al. 27.6 a 25 MHz-BW 75 dB-SNDR inherent gain error tolerance noise-shaping SAR-assisted pipeline ADC with background offset calibration[C]// 2021 IEEE International Solid-State Circuits Conference (ISSCC). Piscataway,NJ: IEEE, 2021: 380-382. [40]MIYAHARA M, ASADA Y, PAIK D, et al. A low-noise self-calibrating dynamic comparator for high-speed ADCs[C]// 2008 IEEE Asian Solid-State Circuits Conference. Piscataway,NJ: IEEE, 2008: 269-272. [41]REYES B T, BIOLATO L, GALETTO A C, et al. A 4 GS/s 8-bit SAR ADC with an energy-efficient time-interleaved architecture in 130 nm CMOS[C]// 2020 Argentine Conference on Electronics (CAE). Piscataway,NJ: IEEE, 2020: 77-81. [42]MA P S, CHEN Y Z, WU J F. A double-latch comparator for multi-GS/s SAR ADCs in 28 nm CMOS[C]// 2019 IEEE 13th International Conference on ASIC (ASICON). Piscataway,NJ: IEEE, 2019: 1-3. [43]SUNG G M, WU P E, XU J M. 10-Bit successive approximation register analog-to-digital converter for BLDC motor drive[C]// 2020 International Symposium on Computer, Consumer and Control (IS3C). Piscataway,NJ: IEEE, 2020: 224-227. [44]SHARUDDIN I, LEE L. Modified SR latch in dynamic comparator for ultra-low power SAR ADC[C]// 2015 IEEE International Circuits and Systems Symposium (ICSyS). Piscataway,NJ: IEEE, 2015: 151-154. [45]KESHATTIWAR A, SAHOO B D. A systematic approach to sizing capacitors in split-SAR ADC to achieve optimum redundancy[C]// 2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS). Piscataway,NJ: IEEE, 2019: 117-120. [46]DING X, HOFMANN K, ZHANG L, et al. Redundant double conversion based digital background calibration of SAR ADC with convergence acceleration and assistance[C]// 2018 25th International Conference “Mixed Design of Integrated Circuits and System” (MIXDES). Piscataway,NJ: IEEE, 2018: 192-197. [47]何生生.一种采用冗余位技术的12位SAR ADC的设计与研究[D].成都:电子科技大学,2019. [48]钟利斌.高精度ADC误差提取与校正技术研究[D].成都:电子科技大学,2021. [49]ZHANG X J, WANG M D, GUO L Y, et al. A 12-bit 200KS/s SAR ADC with digital self-calibration[C]// 2017 IEEE 2nd Advanced Information Technology, Electronic and Automation Control Conference (IAEAC). Piscataway,NJ: IEEE, 2017: 2531-2535. [50]LOPEZ-ANGULO A, GINES A, PERALIAS E. Digital calibration of capacitor mismatch and comparison offset in split-CDAC SAR ADCs with redundancy[C]// 2020 18th IEEE International New Circuits and Systems Conference (NEWCAS). Piscataway,NJ: IEEE, 2020: 130-133. [51]AKKAYA A, CELIK F, LEBLEBICI Y. An 8-bit 800 MS/s loop-unrolled SAR ADC with common-mode adaptive background offset calibration in 28 nm FDSOI[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2021, 68(7): 2766-2774. [52]GINES A, LEGER G, PERALIAS E. Digital non-linearity calibration for ADCs with redundancy using a new LUT approach[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2021, 68(8): 3197-3210. [53]BAGHERI M, SCHEMBARI F, ZARE-HOSEINI H, et al. Interchannel mismatch calibration techniques for time-interleaved SAR ADCs[J]. IEEE Open Journal of Circuits and Systems, 2021, 2: 420-433. [54]PENG X Z, ZHONG Z Q, WU N, et al. A 14 bits 1GSPS pipelined-SAR ADC with digital background calibration[C]// 2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT). Piscataway,NJ: IEEE, 2020: 1-1. [55]CHUNG Y H, HU C Y, CHANG C W. A 38-mW 7-bit 5-GS/s time-interleaved SAR ADC with background skew calibration[C]// 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC). Piscataway,NJ: IEEE, 2018: 243-246. [56]GARVIK H, WULFF C, YTTERDAL T. A 68 dB SNDR compiled noise-shaping SAR ADC with on-chip CDAC calibration[C]// 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC). Piscataway,NJ: IEEE, 2019: 193-194. [57]ZHANG Q H, NING N, LI J, et al. A second-order noise-shaping SAR ADC using two passive integrators separated by the comparator[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2021, 29(1): 227-231. [58]FAN H, WU X J, FENG QY, et al. Capacitive recombination calibration method to improve the performance of SAR ADC[C]// 2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS). Piscataway,NJ: IEEE, 2020: 43-46. [59]YOUN E, JANG Y C. 12-bit 20M-S/s SAR ADC using C-R DAC and capacitor calibration[C]// 2018 International SoC Design Conference (ISOCC). Piscataway,NJ: IEEE, 2018: 1-2. [60]OH D R, MOON K J, LIM W M, et al. An 8-bit 1-GS/s asynchronous loop-unrolled SAR-flash ADC with complementary dynamic amplifiers in 28-nm CMOS[J]. IEEE Journal of Solid-State Circuits, 2021, 56(4): 1216-1226. [61]WU J J, WU J H. Background calibration of capacitor mismatch and gain error in pipelined-SAR ADC using partially split structure[C]// 2021 IEEE 5th Advanced Information Technology, Electronic and Automation Control Conference (IAEAC). Piscataway,NJ: IEEE, 2021: 1882-1885. [62]FAN H, WANG Y N, WU X J. A realizable digital bubble sorting SAR ADC calibration technology[C]// 2021 International Conference on IC Design and Technology (ICICDT). Piscataway,NJ: IEEE, 2021: 1-4. [63]刘振宇,宋树祥,岑明灿,等.低功耗高精度Sigma-Delta调制器的建模与设计[J].广西师范大学学报(自然科学版),2022,40(2):58-70. |
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