低功耗高精度Sigma-Delta调制器的建模与设计

doi:10.16088/j.issn.1001-6600.2021061505

Abstract

Abstract: In order to improve the accuracy of the Sigma-Delta modulator and reduce its power consumption, an improved second-order single-loop CIFF Sigma-Delta modulator is designed. The additional power consumption caused by the number of noise shaping filters is reduced by using op-amp sharing technology. The idea of floating coefficient iteration is applied to the modeling of the modulator in MATLAB, and the specific values of various parameters that meet the precision requirements are finally determined. Through the introduction of non-ideal factors, the obtained parameters are simulated and verified to meet the minimum performance index, and then the transistor level circuit is designed. The modulator has a signal bandwidth of 8 kHz and a sampling frequency of 4 MHz. The circuit design uses UMC 0.11 μm CMOS process, and the core circuit layout size is 226.8 μm×187.44 μm. The post-simulation results show that when the power supply voltage is 1.2 V, the total power consumption of the modulator is 290 μW. At -40-125 ℃, and the effective bits of each process Angle is more than 15 bits.

Key words: sigma-delta modulator, floating coefficient, matlab modeling, low power consumption, high-precision, voice chip

CLC Number:

TN761

LIU Zhenyu, SONG Shuxiang, CEN Mingcan, JIANG Pinqun, CAI Chaobo. Modeling and Design of Low Power and High Precision Sigma-Delta Modulator[J].Journal of Guangxi Normal University(Natural Science Edition), 2022, 40(2): 58-70.

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Modeling and Design of Low Power and High Precision Sigma-Delta Modulator

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